1. Field of the Invention
The present invention relates to a method of processing an additional layer such as an insulating film formed on the front side of a wafer such as a semiconductor wafer.
2. Description of the Related Art
In a semiconductor device such as a main computing device (MPU) and a memory device (e.g., DRAM) for a computer, the scale of integration is increased with a reduction in size and thickness of various electronic equipment incorporating the semiconductor device. Such a semiconductor device can be obtained by forming many devices on the front side of a semiconductor wafer such as a silicon wafer and separating the wafer into these devices. With an increase in scale of integration in a semiconductor device, it becomes necessary to form a multilayer structure of wiring layers on the front side of the wafer in order to further increase the scale of integration, increase an operating speed, and ensure design flexibility. In the case of forming such a multilayer structure of wiring layers, these wiring layers stacked must be insulated from each other, and an insulating film is therefore formed on the upper surface of each wiring layer by any film deposition method such as chemical vapor deposition (CVD) and spin coating.
The insulating film is first planarized by any method such as chemical mechanical polishing (CMP), and the wiring layer is next formed on the upper surface of the insulating film by photolithography. By repeating this process, a multilayer structure of wiring layers is formed on the wafer. If the insulating film is not planarized, a focal position of light on the insulating film in an exposure step of the photolithography does not become constant, so that the thickness of each wire does not become constant. For this reason, the insulating film must be planarized prior to forming the wiring layer. As a technique of planarizing the insulating film, a cutting method using a bit is known (see Japanese Patent Laid-open No. 9-82616). Also known is a cutting method including the step of flat grinding the back side of a wafer functioning as a reference surface in cutting the insulating film by using a bit, so as to improve the flatness of the insulating film (see WO2004-053967).
In recent years, the thickness of an insulating film having a low dielectric constant tends to be increased, so that the amount of processing of the insulating film is increased. Accordingly, if the insulating film is processed by only CMP, a processing cost is increased in proportion to the amount of processing. In the case that the insulating film is cut by using a bit to reduce the thickness as in the prior art mentioned above, the processing cost can be reduced as compared with the case of adopting only CMP. However, the flatness (smoothness) of the finished surface of the insulating film by the cutting using the bit is lower than that by CMP. Further, in the case of cutting the insulating film by using the bit, the wafer is fixed to a holding table with reference to the back side of the wafer, and the front side of the wafer is cut in this fixed condition. Accordingly, the cutting using the bit is not suitable for such processing that the thickness of the insulating film is made constant with reference to the front side of the wafer.